The present invention relates to a semiconductor apparatus, in particular, a semiconductor apparatus suitable for preventing the deterioration of the data processing performance.
As the semiconductor manufacturing process has been miniaturized, the scale of a circuit that can be mounted on one semiconductor chip is increasing. As a result, in logic LSIs, a large number of functional blocks necessary for the system can be mounted on one semiconductor chip. Therefore, a larger number of data processes are carried out in a logic LSI. Because of this trend, it has been required to improve data transfer performance between a logic LSI and a memory and thereby improve the overall data processing performance of the system.
Further, it has become more common to incorporate a functional block that processes data having a data width larger than the maximum data width with which the memory can simultaneously read/write data, into a logic LSI. Even in such situations, it has been desired to improve the data transfer performance between the logic LSI and the memory and thereby improve the overall data processing performance of the system.
Japanese Unexamined Patent Application Publications No. 9-231131 and No. 2009-230776 disclose related art.
A memory having a variable data width disclosed in Japanese Unexamined Patent Application Publication No. 9-231131 is constructed by combining four memories, and thereby can change its processible data width to 8, 16, or 32 bits.
A multi-port memory disclosed in Japanese Unexamined Patent Application Publication No. 2009-230776 is equipped with a path switching circuit capable of arbitrarily configuring signal paths of a command, an address, and input/output data between a plurality of input/output ports and a plurality of memory banks, and thereby can allocate a plurality of arbitrarily-selected input/output ports to a selected memory bank.